CELL-BASED FULLY INTEGRATED CMOS FREQUENCY-SYNTHESIZERS

A family of standard cells for phase-locked loop (PLL) applications is presented. The applications are processed using a 1.5 mum, n-well, do uble-polysilicon, double-layer metal CMOS process. Applications includ e frequency synthesis for computer clock generation, disk drives, and pixel clock generators for computer monitors, with maximum frequencies up to 80 MHz. The synthesizers require no external components since t he loop filter and oscillator are on chip with the phase frequency det ector and the charge pump. Special voltage and current reference cells are discussed. Analysis of noise sources in the PLL demonstrates the need for reducing the phase noise of the system. A low phase noise is achieved through supply rejection techniques and by placing the oscill ator in a high-gain feedback loop to minimize its noise contributions. Laboratory measurements of completed silicon show synthesizers with e xceptionally linear gain, as well as transient responses and phase noi se similar to predicted results.