AN OUTLINE FONT RENDERING PROCESSOR WITH AN EMBEDDED RISC CPU FOR HIGH-SPEED HINT PROCESSING

Citation
T. Kawata et al., AN OUTLINE FONT RENDERING PROCESSOR WITH AN EMBEDDED RISC CPU FOR HIGH-SPEED HINT PROCESSING, IEEE journal of solid-state circuits, 29(3), 1994, pp. 280-289
Citations number
14
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
00189200
Volume
29
Issue
3
Year of publication
1994
Pages
280 - 289
Database
ISI
SICI code
0018-9200(1994)29:3<280:AOFRPW>2.0.ZU;2-Q
Abstract
Font rendering requires state-of-the-art hint processing for delicate adjustment to output devices in practical applications. The hint proce ssing is a function which corrects transformed outlines using addition al information. A font rendering processor has been developed using a CMOS 0.8 mum pg process on a 9.47 x 9.24 mm2 die. It incorporates the hint processing capability, and thus unburdens a host CPU of the whole font rendering. It comprises a RISC CPU for high-speed hint processin g and special hardware units that is based upon a DDA and an edge flag algorithm for outline drawing and filling. A performance evaluation u sing the fabricated chip has shown about 0.4 ms/char and 1.5 ms/char r endering capability for small size alphabets and Kanji's, respectively . It equals about 7-11 times performance compared to a Sparc Station 2 , and from about 22-38 times performance compared to a Sun4/110.