3.3V BICMOS CIRCUIT TECHNIQUES FOR A 120MHZ RISC MICROPROCESSOR

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RIS C microprocessor. The processor is implemented in a 0.5-mum BiCMOS tec hnology with 4-metal-layer structure. The chip includes a 240 MFLOPS f ully pipelined 64-b floating point datapath, a 240-MIPS integer datapa th, and 24KB cache, and contains 2.8 million transistors. The processo r executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense ampl ifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are ap plied to the processor. The processor with the proposed BiCMOS circuit s has a 11%-47% shorter delay time advantage over a CMOS microprocesso r.