DESIGN TECHNIQUES FOR LOW-VOLTAGE HIGH-SPEED DIGITAL BIPOLAR CIRCUITS

This paper describes design techniques for multigigahertz digital bipo lar circuits with supply voltages as low as 1.5 V. Examples include a 2/1 multiplexer operating at 1 Gb/s with 1.2 mW power dissipation, a D -latch achieving a maximum speed of 2.2 GHz while dissipating 1.4 mW, two exclusive-OR gates with a delay less than 200 ps and power dissipa tion of 1.3 mW, and a buffer/level shifter having a delay of 165 ps wh ile dissipating 1.4 mW. The prototypes have been fabricated in a 1.5-m um 12-GHz bipolar technology. Simulations on benchmarks such as freque ncy dividers and line drivers indicate that for a 1.5-V supply, the pr oposed circuits achieve higher speed than their CMOS counterparts desi gned in a 0.5-mum CMOS process with zero threshold voltage.