A SAMPLING TECHNIQUE AND ITS CMOS IMPLEMENTATION WITH 1 GB S BANDWIDTH AND 25 PS RESOLUTION/

This paper presents a technique and circuitry for high-resolution samp ling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through dela y elements in such a way that resolution is controlled by the differen ce in the delay of clock and data signals. Delay units were designed u sing biased CMOS and differential CMOS inverters. A sampler circuit wi th 64 stages has been fabricated in 1.2 mum CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a samp ling resolution externally adjustable between 25 and 250 ps. The fabri cated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution.