CONE BLOCK METHODS FOR LOGIC SIMULATION TIME REDUCTION IN E-BEAM GUIDED-PROBE DIAGNOSIS

Cone and Block methods that sharply reduce logic simulation time in E- beam guided-probe diagnosis are proposed. These methods are based on a primitive-cell-level tracing algorithm, which traces faulty-state cel ls one by one in the primitive-cell level. By executing logic simulati ons in these methods so that simulated responses are reported only for the small set of nodes in a tracing path and in the immediate vicinit y, simulation CPU time is sharply reduced with state-of-the-art logic simulators such as the Verilog-XL. With the proposed methods, the tota l CPU time in a diagnostic process can be reduced to 1/700 that of a c onventional method. Additionally, the total amount of simulation data also reduces to 1/40 of its original amount. These methods were applie d to the guided-probe diagnosis of actual 110k-gate ASIC chips and it was verified that they could be diagnosed in under seven hours per dev ice, which is practical. This technology will greatly contribute to sh ortening the turnaround time of ASIC development.