4-2 COMPRESSOR WITH COMPLEMENTARY PASS-TRANSISTOR LOGIC

This report describes 4-2 compressors composed of Complementary Pass-T ransistor Logic (CPL). We will show that circuit designs of the 4-2 co mpressors can be optimized for high speed and small size using only ex clusive-OR's and multiplexers. According to a circuit simulation with 0.8 mum CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, resp ectively.