New gate logics, standby/active mode logic I and II, for future 1 G/4
Gb DRAM's and battery operated memories are proposed. The circuits rea
lize sub-1-V supply voltage operation with a small 1-muA standby subth
reshold leakage current, by allowing 1 mA leakage in the active cycle.
Logic I is composed of logic gates using dual threshold voltage (Vt)
transistors, and it can achieve low standby leakage by adopting high V
t transistors only to transistors which cause a standby leakage curren
t. Logic II uses dual supply voltage lines, and reduces the standby le
akage by controlling the supply voltage of transistors dissipating a s
tandby leakage current. The gate delay of logic I is reduced by 30-37%
at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is
reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to
that of the conventional CMOS logic.