MEMORY ARRAY ARCHITECTURE AND DECODING SCHEME FOR 3-V ONLY SECTOR ERASABLE DINOR FLASH MEMORY

A memory array architecture and row decoding scheme for a 3 V only DIN OR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative volta ge switching row decoder and a compact source line driver have been de veloped for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection c ircuit provide a high speed random access time at low V(cc) and a narr ow program threshold voltage distribution. A 4 Mb DINOR flash memory t est device was fabricated from 0.5 mum, double-layer metal, triple pol ysilicon, triple well CMOS process. The cell measures 1.8 x 1.6 mum2 a nd the chip measures 5.8 x 5.0 mm2. The divided bit line structure rea lizes a small NOR type memory cell.