AN EFFICIENT BACK-BIAS GENERATOR WITH HYBRID PUMPING CIRCUIT FOR 1.5-V DRAMS

An efficient back-bias (V(bb)) generator with a newly introduced hybri d pumping circuit (HPC) is described. This system attains a V(bb) leve l of - 1.44 V at V(cc) = 1.5 V, compared to a conventional system in w hich V(bb) only reaches -0.6 V. HPC can pump without the threshold vol tage (V(th)) loss that conventional systems suffer. HPC is indispensab le for 1.5-V DRAM's, because a V(bb) level lower than - 1.0 V is neces sary to meet the limitations of the V(th) of the access transistor. HP C uses one NMOS and one PMOS pumping transistor. By adopting a triple- well structure at the pumping circuit area, the NMOS can be employed a s a pumping transistor without minority carrier injection.