THRESHOLD VOLTAGE SHIFT OF AMORPHOUS-SILICON THIN-FILM TRANSISTORS WITH ATMOSPHERIC-PRESSURE CHEMICAL-VAPOR-DEPOSITION SILICON DIOXIDE

The threshold voltage (V(th)) shift of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) have been investigated for the atm ospheric pressure chemical vapor deposition (APCVD) silicon dioxide (S iO2) gate insulator. For both positive and negative gate bias stress, the threshold voltage was shifted in the positive direction and was do minated by the defect creation near the a-Si:H/SiO2 interface. There w as little charge trapping into the APCVD SiO2 gate insulator under the gate bias stress. For the positive gate bias stress, the threshold vo ltage shifts of a-Si:H TFTs with the a-Si:H/SiO2 interface were smalle r than those of the conventional a-Si:H TFTs with the a-Si:H/SiN(x) in terface.