FAST PARALLEL ALGORITHM FOR TERNARY MULTIPLICATION USING MULTIVALUED I2L TECHNOLOGY

Authors
DE M SINHA BP
Citation
M. De et Bp. Sinha, FAST PARALLEL ALGORITHM FOR TERNARY MULTIPLICATION USING MULTIVALUED I2L TECHNOLOGY, I.E.E.E. transactions on computers, 43(5), 1994, pp. 603-607
Citations number
28
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
Journal title
I.E.E.E. transactions on computers → ACNP
ISSN journal
00189340
Volume
43
Issue
5
Year of publication
1994
Pages
603 - 607
Database
ISI
SICI code
0018-9340(1994)43:5<603:FPAFTM>2.0.ZU;2-D
Abstract
An algorithm for parallel multiplication of two n-bit ternary numbers is presented in this brief contribution. This algorithm uses the techn ique of column compression and computes the product in (2[log2 n] + 2) units of addition time of a single-bit ternary full adder. This algor ithm requires regular interconnection between any two types of cells a nd hence is very suitable for VLSI implementation. The same algorithm is also applicable to the multiplication of negative numbers.