The thermal conductivities of two polycrystalline silicon layers as pr
oduced by a commercial CMOS IC process are reported for the temperatur
e range of 100 to 430 K. One layer, n-doped with a sheet resistance of
25 OMEGA/sq., has a thermal conductivity kappa(n) of 29 W/mK at 300 K
. The second layer, p-doped with a sheet resistance of 225 OMEGA/sq.,
has a thermal conductivity kappa(p) of 18 W/mK at 300 K. These values
were obtained with micromechanical test structures fabricated with a c
ommercial CMOS IC process, and post-processed by anisotropic etching.
The one-dimensional model used to calculate the thermal conductivities
from the raw experimental data was validated by the simulation of the
three-dimensional temperature field in the test structures with the f
inite element simulation program SESES.