BICMOS CIRCUIT TECHNOLOGY FOR A 704 MHZ ATM SWITCH LSI

This paper describes BiCMOS level-converter circuits and clock circuit s that increase VLSI interface speed to 1 GHz, and their application t o a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce i nternal operation speed. A MUX/DEMUX with minimum power dissipation an d a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inve rters and a voltage regulator circuit, can convert signal levels betwe en LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit cons isting of a pure ECL path and retiming circuits. The clock circuit red uces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circu its. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0. 5 mum BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation spee d of 704-MHz with power dissipation of 7.2 W.