A 1.5-V BICMOS DYNAMIC LOGIC-CIRCUIT USING A BIPMOS PULL-DOWN STRUCTURE FOR VLSI IMPLEMENTATION OF FULL ADDERS

Authors
KUO JB CHEN SS CHIANG CS SU KW LOU JH
Citation
Jb. Kuo et al., A 1.5-V BICMOS DYNAMIC LOGIC-CIRCUIT USING A BIPMOS PULL-DOWN STRUCTURE FOR VLSI IMPLEMENTATION OF FULL ADDERS, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 41(4), 1994, pp. 329-332
Citations number
17
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE transactions on circuits and systems. 1, Fundamental theory andapplications → ACNP
ISSN journal
10577122
Volume
41
Issue
4
Year of publication
1994
Pages
329 - 332
Database
ISI
SICI code
1057-7122(1994)41:4<329:A1BDLU>2.0.ZU;2-9
Abstract
This paper presents a 1.5 V BiCMOS dynamic logic circuit using a ''BiP MOS pull-down'' structure, which is free from race problems, for VLSI implementation of full adders. Using the 1.5 V BiCMOS dynamic logic ci rcuit, a 16-bit full adder circuit, which is composed of half adders a nd a carry look-ahead circuit, shows a 1.7 times improvement in speed as compared to the CMOS static one.