STRUCTURAL AND BEHAVIORAL SYNTHESIS FOR TESTABILITY TECHNIQUES

In this paper, a behavioral synthesis for testability system is presen ted. In this system, a testability modifier is connected to an existin g behavioral level synthesis program, which accepts a circuit's behavi oral description in C or VHDL as input. The outline of the system is a s follows: (1) a testability analyzer is first applied to identify the hard-to-test areas in the circuit from the behavioral description; (2 ) a selection process is then applied to select test points or partial scan flip-flops. Selection is based on behavioral information rather than low-level structural description. This allows Test Point Insertio n or Partial Scan usage on circuits described as an interconnection of high level modules; (3) Test Statement Insertion (TSI), an alternativ e to Test Point Insertion and Partial Scan, is used to modify the circ uit based on the selected test points. The major advantage of using Te st Statement Insertion is a low pin count and test application time as compared to Test Point Insertion and Partial Scan. In addition, TSI c an be applied at the early design phase. This approach was implemented in a computer program, and applied to several sample circuits generat ed by a synthesis tool. The results are also presented.