EVENT SUPPRESSION - IMPROVING THE EFFICIENCY OF TIMING SIMULATION FORSYNCHRONOUS DIGITAL CIRCUITS

Timing simulation is a widely used method to verify the timing behavio r of a design. In a synchronous digital system the timing property tha t needs to be verified is that there is no event at the outputs of the combinational parts of the circuit at or after time tau, the clock pe riod. In this paper we first show that conventional timing simulation applied to this problem has exponential complexity. Next we demonstrat e that for this problem a complete history of circuit activity before time tau is not needed. We exploit this observation and present an eve nt suppression method that potentially leads to an exponential reducti on in the number of events that need to be processed during simulation . This is backed by encouraging experimental results.