D-CPT - A TIME-SPACE EFFICIENT FAULT SIMULATOR

Citation
Wd. Li et al., D-CPT - A TIME-SPACE EFFICIENT FAULT SIMULATOR, International journal of electronics, 76(4), 1994, pp. 633-645
Citations number
10
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
00207217
Volume
76
Issue
4
Year of publication
1994
Pages
633 - 645
Database
ISI
SICI code
0020-7217(1994)76:4<633:D-ATEF>2.0.ZU;2-P
Abstract
A new fault simulation method, deductive critical path tracing (D-CPT) , for very large combinational circuits is proposed. The simulator use s both the deductive fault propagation technique (used in deductive fa ult simulation (DFS)) and the critical path tracing (CPT) method in fo rming the D-CPT. Deductive fault propagation is not performed on the w hole fault set of a circuit as in DFS but instead only on a partial fa ult set, i.e., those faults on fanout stems. The capture lines of each fanout fault are determined, and used to resolve the difficulty in de termining the criticality of a fanout stem during the CPT process. Fur thermore. the huge storage requirement of DFS is sharply reduced to an acceptable level when handling very large circuits. Experiments on IS CAS benchmark circuits show that the proposed method is both efficient and complete.