LATCH AND HOT-ELECTRON GATE CURRENT IN ACCUMULATION-MODE SOI P-MOSFETS

Simultaneous measurements of drain and gate currents in short-channel accumulation-mode SOI p-MOSFET'MOs demonstrate that a latch mechanism may occur in these devices and induce an anomalous behavior of the hot -electron gate current: distortion of I(g)(V(g)) curves, hysteresis an d excessively high gate current values. 2-D MEDICI simulations based o n the lucky-electron model qualitatively reproduce the measurements in the latch regime, and explain the unusual gate current dependence on drain and gate biases. The results are of relevance for reliability an d modeling issues.