A 110-MHZ 1-MB SYNCHRONOUS TAGRAM

A 4-way set associative TagRAM with 1.189-Mb capacity has been develop ed which can handle a secondary cache system of up to 16 Mbytes. A 9-n s cycle operation and clock to D(out) of 4.7 ns are achieved by use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, doubl y placed self-timed write circuits, and highly linear VCO for a PLL. T he device is successfully implemented with 0.7-mum double polysilicon double-metal BiCMOS technology.