A 1.5-NS CYCLE-TIME 18-KB PSEUDO-DUAL-PORT RAM WITH 9K LOGIC GATES

An 18-kb RAM with 9-kgate control logic gates operating during a cycle -time of 1.5 ns has been developed. A pseudo-dual-port RAM function is achieved by a two-bank structure and on-chip control logic. Each bank can operate individually with different address synchronizing the sin gle clock. A sense-amplifier with a selector function reduces the read ing propagation time. Bonded SOI wafers reduce the memory-cell capacit ance, and this results in a fast write cycle without sacrificing alpha -particle immunity. The chip is fabricated in a double polysilicon sel f-aligned bipolar process using trench isolation. The minimum emitter size is 0.5 x 2 mum2 and the chip size is 11 x 11 mm2.