250 MBYTE S SYNCHRONOUS DRAM USING A 3-STAGE-PIPELINED ARCHITECTURE/

A 3.3-V 512-k x 18-b x 2-bank synchronous DRAM (SDRAM) has been develo ped using a novel 3-stage-pipelined architecture. The address-access p ath which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standard ized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 11 3.7-mm2, which is the same die size as our conventional DRAM, has been achieved with 0.50-mum CMOS process technology.