16-MB SYNCHRONOUS DRAM WITH 125-MBYTE S DATA RATE/

Authors
CHOI Y KIM M JANG H KIM T LEE S LEE H PARK C LEE S KIM C CHO S HAQ E KARP J CHIN D
Citation
Y. Choi et al., 16-MB SYNCHRONOUS DRAM WITH 125-MBYTE S DATA RATE/, IEICE transactions on electronics, E77C(5), 1994, pp. 859-863
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEICE transactions on electronics → ACNP
ISSN journal
09168524
Volume
E77C
Issue
5
Year of publication
1994
Pages
859 - 863
Database
ISI
SICI code
0916-8524(1994)E77C:5<859:1SDW1S>2.0.ZU;2-E
Abstract
In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDR AM has programmable latency, burst length, and burst type for wide var iety of applications. The experimental 16M SDRAM (2M x 8) achieves a 1 25-Mbyte/s data rate using 0.5-mum twin well CMOS technology.