An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed
. This BL arrangement offers small die size and good array noise immun
ity. In this arrangement, one BL of an open BL pair is placed in betwe
en a folded BL pair, and the sense amplifiers (SA's) for open BL's and
those for folded BL's are placed alternately between the memory array
s. This arrangement features a small 6F2 memory cell, where F is the d
evice feature size, and a relaxed SA pitch of 6F. The die size of a 64
-Mb DRAM can be reduced to 81.6% compared with the one using the conve
ntional folded BL arrangement. The BL-BL coupling noise is reduced to
one-half of that of the conventional folded BL arrangement, thanks to
the shield effect. Two new circuit techniques, 1) a multiplexer for co
nnecting BL's to SA's, and 2) a binary-to-ternary code converter for t
he multiplexer have been developed to realize the new BL arrangement.