20GBIT S DR BASED TIMING RECOVERY CIRCUIT

Authors
MONTEIRO P MATOS JN GAMEIRO A DAROCHA JRF
Citation
P. Monteiro et al., 20GBIT S DR BASED TIMING RECOVERY CIRCUIT, Electronics Letters, 30(10), 1994, pp. 799-800
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
30
Issue
10
Year of publication
1994
Pages
799 - 800
Database
ISI
SICI code
0013-5194(1994)30:10<799:2SDBTR>2.0.ZU;2-T
Abstract
The design and characterisation of a 20 Gbit/s clock recovery unit dev eloped for the RACE 2011 project of the European Community is reported . This unit is based on an open loop structure using a dielectric reso nator narrowband filter. The jitter results show that the approach pro vides a robust and low cost solution for the clock extraction problem at very high bit rates.