A BURIED CAPACITOR CELL WITH BONDED SOI FOR 256-MBIT AND 1-GBIT DRAMS

A new DRAM cell structure for 256-Mbit and 1-Gbit DRAMs has been devel oped in which the cell capacitors are flexibly formed like a stacked c apacitor (STC), but are buried under the thin silicon layer of a bonde d SOI substrate. As a result, both large capacitance (C(s)) and small cell size are realized. Using a 0.4-mum design rule, 1.28-mum2 memory cells with a C(s) of 47 fF are successfully fabricated with a large al ignment tolerance of 0.2 mum. Moreover, the leakage current is reduced to less than 1 fA per cell, resulting in good data retention.