CLOCK DISTRIBUTION IN GENERAL VLSI CIRCUITS

Minimization of clock skew in VLSI circuits to within a tolerable rang e is important for dependable operation of any digital system. Moreove r, excessive delay through a clock distribution network can significan tly degrade the performance of the digital system. Differences in path lengths and active elements of a clock distribution network are large ly responsible for clock skew while excessive delay is a result of ver y long signal routes in the network. Improved integrated circuit proce sses are placing an increasing demand on current clock routing schemes through higher clock rates and larger die sizes. This paper proposes a clock routing scheme that primarily minimizes clock skew in a genera l VLSI circuit whose functional elements may be of various sizes and p lacements. A secondary objective is to reduce the overall network dela y. The clock distribution network is generated based on the analysis o f RC trees. In the networks so generated, the delay seen from the cloc k entry point of a circuit to all modules within the circuit is nearly identical. In constructing the clock distribution networks, the fan o ut of a buffer is accounted for and flexibility in placement of buffer s is utilized.