HIGHLY TESTABLE DESIGN OF BICMOS LOGIC-CIRCUITS

Most of the work reported in the literature to date on the testability of BiCMOS circuits has concentrated on fault characterization and the need for a suitable testing method that can address the peculiarities of BiCMOS circuits. The problem of adequately testing large BiCMOS lo gic networks remains open and complex. In this paper, we introduce a n ew design for testability technique for BiCMOS logic gates that result s in highly testable BiCMOS logic circuits. The proposed design incorp orates two features: a test charge/discharge path and built-in current sensing (BICS). The test charge/discharge path is activated only duri ng testing and facilitates the testing of stuck-open faults using sing le test vectors. BICS facilitates testing of faults that cause excessi ve IDDQ. HSPICE simulation results show that the proposed design can d etect stuck-open faults at a test speed of 10 MHz. Faults causing exce ssive IDDQ are detected by BICS with a detection time of 1 ns and a se ttling time of 2 ns. Impact of the proposed design on normal operation is minimal. The increase in propagation delay in normal operation is less than 3%. This compares very favorably with CMOS BICS reported in the literature [22], [23] where the propagation delay increase was 20% , 14.4% respectively. The increase in the area is less than 15%.