A CHARGE RECYCLE REFRESH FOR GB-SCALE DRAMS IN FILE APPLICATIONS

A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstra ted using a 64 kb test chip with 0.25 mum technology. After amplificat ion in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh oper ation, and the voltage bounce of the power supply line is 60% of the c onventional. This scheme is further extended for application to n arra ys with 1/n data-line current dissipation. Moreover, the multi-array a ctivation with Charge Recycle Refresh is proposed, in which the same p eak current as in the conventional scheme is achieved with a small num ber of refresh cycles for refreshing all the cells.