A 4-QUADRANT CMOS ANALOG MULTIPLIER FOR ANALOG NEURAL NETWORKS

A four-quadrant CMOS analog multiplier is presented. The multiplier us es the square-law characteristic of an MOS transistor in saturation. I ts major advantage over other four-quadrant multipliers is its combina tion of small area and low power consumption. In addition, unlike almo st all other designs of four-quadrant multipliers, this design has sin gle ended inputs so that the inputs do not need to be pre-processed be fore being fed to the multiplier, thus saving additional area. These p roperties make the multiplier very suitable for use in the implementat ion of artificial neural networks. The design was fabricated through M OSIS using the standard 2 mum CMOS process. Experimental results obtai ned from it are presented.