A COMMUNICATION ARCHITECTURE TAILORED FOR ANALOG VLSI ARTIFICIAL NEURAL NETWORKS - INTRINSIC PERFORMANCE AND LIMITATIONS

An architecture for interchip communication among analog VLSI neural n etworks is proposed. Activity is encoded in a neuron's pulse emission frequency. Information is transmitted through the non-arbitered, async hronous access of pulses to a common bus. The impact of collisions whe n the bus is accessed by more than one user is investigated. The infor mation-carrying capability is.assessed and the trade-off between accur acy of the transmitted information and attainable dynamic range is bro ught out in terms of simple global parameters that characterize the ap plication. It is found that the proposed architecture is well suited f or the kind of communication requirements associated to neural computa tion systems. A coding scheme aimed at pushing the system towards its theoretical performance is also presented and evaluated.