A FAST METHOD TO EVALUATE THE OPTIMUM NUMBER OF SPARES IN DEFECT-TOLERANT INTEGRATED-CIRCUITS

In this paper, we present a method to accelerate the search for the nu mber of spares to be included in defect-tolerant integrated circuits. Our method is obtained by bringing two modifications to a conventional evaluation method. The main motivations behind the development of thi s method are: the possibilities offered by the implementation of defec t tolerance, the existence of many yield models, which may predict dif ferent results in terms of optimum number of spares, and the fact that some models are very compute intensive. The modeling methods leading to several usual yield models are briefly presented here. We also pres ent results showing that our method is valid for a wide range of param eters. Moreover, this method can be applied to all yield models consid ered here and it can significantly reduce the time spent in the search for the best possible reconfiguration strategies.