Sw. Cheng et al., THE ROLE OF LONG AND SHORT PATHS IN-CIRCUIT PERFORMANCE OPTIMIZATION, IEEE transactions on computer-aided design of integrated circuits and systems, 13(7), 1994, pp. 857-864
In this paper, we consider the problem of determining the smallest clo
ck period for a combinational circuit. By considering both the long an
d short paths, we derive three independent bounds on the clock period.
The first bound is the difference between the longest path delay and
the shortest path delay, which has been studied before [6], [9], [11],
[12]. The other two take the functionality of the circuit into consid
eration and, therefore, is usually smaller than the first one. To brin
g in the functionality of the circuit, we make use of a new class of p
aths-called the shortest destabilizing paths-as well as the longest se
nsitizable paths. We also show that considering both the longest sensi
tizable path and the shortest destabilizing path together does not alw
ays give a valid bound. The bounds on the clock period can be alternat
ively viewed as optimization objectives. At the physical level, the co
mplexity of optimization very much depends on the number of long and s
hort paths present and the number of gates shared by them. We conducte
d preliminary experiments to study this.