ADDRESSING DESIGN FOR TESTABILITY AT THE ARCHITECTURAL LEVEL

The increasing use of hardware description languages (HDL's) in VLSI d esign and the emergence of high-level test generation programs has led to an interesting problem. There is a need for design for testability (DFT) techniques that can be applied early in the design phase to imp rove the effectiveness of ATPG programs on hard-to-test circuits. By a n early identification of hard-to-test areas of a circuit, testability can be inserted prior to logic synthesis. In this paper, we first pre sent a comparative study of a gate-level test generator and a high-lev el test generator by benchmarking them on a common suite of circuits. Based on an evaluation of the results, we propose techniques to automa tically extract information from the high-level circuit description th at could improve the performance of both ATPG tools. An automatic DFT tool that utilizes VHDL descriptions of the circuit to make an intelli gent selection of flip-flops for partial scan is then described. Resul ts on six hard-to-test circuits show that very high fault coverages ca n be obtained by both a gate-level and a high-level test generator on these circuits after scan. With this detailed study we demonstrate tha t a DFT tool can make a more efficient and effective selection of part ial scan flip-flops by exploiting the high-level circuit information. It can accurately predict the hard-to-test areas of a circuit. Signifi cant improvements in fault coverage and ATPG efficiency, and speedups in ATPG time, can be obtained by a gate-level and a high-level test ge nerator after high-level scan selection.