A 10-B, 100-MS S CMOS A D CONVERTER

A new architecture for a CMOS A/D converter overcomes many of the know n problems in the parallel operation of multiple pipelined stages, The input signal is sampled in one channel, and after quantization to 4 b , the residue is distributed into many channels, A prototype implement ed in 1-mu m CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greate r than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same.