STRUCTURED DESIGN OF A 288-TAP FIR FILTER BY OPTIMIZED PARTIAL PRODUCT TREE COMPRESSION

A compact 10-b, 288-tap finite impulse response (FIR) filter is design ed by adopting structured architecture that employs an optimized parti al product tree compression method, The new scheme is based on the add ition of equally weighted partial products resulted from 288 multiplic ations of the filter coefficients and the inputs, The 288 multiplicati on and 287 addition operations are decomposed to add 1440 partial prod ucts and the sign extension operations are manipulated independently t o ensure the operation at 72 MHz, the internal clock frequency generat ed by the integrated phase-locked loop (PLL) clock multiplier, In addi tion to the optimized transmission gate full adder, modified carry sav e compression circuits such as 4:2 and 5:5:2 compressors are used to p erform decomposed partial product addition, This structured approach e nables cascade design that requires more than 288-tap FIR filtering, T he completed 288-tap FIR filter core occupies 5.36x 7.29 mm(2) of sili con area that consists of 371732 transistors in 0.6-mu m triple-metal CMOS technology, and it consumes only 0.8 W of average power at 3.3 V.