HIGH-SPEED HIGH-BANDWIDTH DESIGN METHODOLOGIES FOR ON-CHIP DRAM CORE MULTIMEDIA SYSTEM LSIS/

Recently, as multimedia large scale integrators (LSI's) have developed , there has been strongly increased demand for high-speed/high-band wi dth LSI's which integrate the DRAM core and logic elements (CPU etc.), However, the high-speed/high-bandwidth operation induces the large sw itching noise, This noise degrades the DRAM's operating margin, and es pecially its data retention characteristics. In this paper, we analyze the noise transmission model and propose DRAM and logic compatible de sign methodologies tb maintain the reliability of high-speed/high-band width system LSI's. We also show that good experimental results are ob tained on the test device, Furthermore, we propose the most suitable I V-DD/GND line scheme for on chip DRAM system LSI.