PARALLEL MODIFIED SIGNED-DIGIT ARITHMETIC USING AN OPTOELECTRONIC SHARED CONTENT-ADDRESSABLE-MEMORY PROCESSOR

Addition is the most primitive arithmetic operation in digital computa tion. Other arithmetic operations such as subtraction, multiplication, and division can all be performed by addition together with some logi c operations. With the binary number system, addition speed is inevita bly limited by the carry-propagation schemes. On the other hand, carry -free addition is possible when the modified signed-digit (MSD) number representation is used. We propose a novel optoelectronic scheme to h andle the parallel MSD addition and subtraction operations. An optoele ctronic shared content-addressable memroy is introduced. The shared co ntent-addressable memory uses free-space optical processing to handle the large amount of parallel memory access operations and uses electro nics to postprocess and derive logic decisions. We analyze the accurac y that the required optical hardware can deliver by using a statistica l cross-talk-rate model that we propose. We also evaluate other import ant device and system performance parameters, such as the memory capac ity or the maximum number of parallel bits the adder can handle in ter ms of a given cross-talk rate at a certain repetition rate, the corres ponding diffraction-limited memory density, and the system's power eff iciency. To confirm the underlining operational principles of the prop osed optoelectronic shared content-addressable-memory MSD adder, we de sign and perform initial experiments for handling 8-bit MSD number add ition and subtraction and present the results.