A DRIVE-LEVEL ERROR RATE MODEL FOR COMPONENT DESIGN AND SYSTEM EVALUATION

A drive-level model for gated peak detection channels in the presence or off-track interference is presented. Input to the model can be digi tized readback patterns from testers, disk drives, or recording proces s simulations. The model predicts bit error rate as a function of ampl itude qualification threshold in the form of a threshold error rate (T ER) plot. Data patterns are described which increase the likelihood of the three types or errors in gated peak detection disk drives: drop-i ns, drop-outs and shifted bits. The importance of designing for drive- level performance, rather than component-level performance is discusse d. Examples of using the model to determine design targets for bead, m edia and channel parameters are given for inductive and magnetoresisti ve applications. The optimum design targets for some key parameters ar e found to change in the presence of off-track interference.