SCALING OF MOS TECHNOLOGY TO SUBMICROMETER FEATURE SIZES

Authors
Citation
Ca. Mead, SCALING OF MOS TECHNOLOGY TO SUBMICROMETER FEATURE SIZES, Analog integrated circuits and signal processing, 6(1), 1994, pp. 9-25
Citations number
35
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
ISSN journal
09251030
Volume
6
Issue
1
Year of publication
1994
Pages
9 - 25
Database
ISI
SICI code
0925-1030(1994)6:1<9:SOMTTS>2.0.ZU;2-W
Abstract
Industries based on MOS technology now play a prominent role in the de veloped and the developing world. More importantly, MOS technology dri ves a large proportion of innovation in many technologies. It is likel y that the course of technological development depends more on the cap ability of MOS technology than on any other technical factor. Therefor e, it is worthwhile investigating the nature and limits of future impr ovements to MOS fabrication. The key to improved MOS technology is red uction in feature size. Reduction in feature size, and the attendant c hanges in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and his torical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on t he system-level implications of feature size as the minimum size appro aches physical limits.