CHARACTERIZATION OF SUBTHRESHOLD MOS MISMATCH IN TRANSISTORS FOR VLSISYSTEMS

MOS transistor mismatch is revisited in the context of subthreshold op eration and VLSI systems. We report experimental measurements from lar ge transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400 mum2) . These are fabricated at different production qualified facilities in 40-nm gate oxide, n-well and p-well, mask lithography processes. Within the small area of our t est-strips (3 mm2), transistor mismatch can be classified into four ca tegories: random variations, ''edge,'' ''striation,'' and ''gradient'' effects. The edge effect manifests itself as a dependence of the tran sistor current on its position with reference to the surrounding struc tures. Contrary to what was previously believed, edge effects extend b eyond the outer most devices in the array. The striation effect exhibi ts itself as a position-dependent variation in transistor current foll owing a sinusoidal oscillation in space of slowly varying frequency. T he gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.