PERFORMANCE ANALYSIS OF MULTILEVEL BUS NETWORKS FOR HIERARCHICAL MULTIPROCESSORS

A multiple bus system provides more bandwidth and a high degree of fau lt tolerance than a single bus system. But such a system becomes very expensive for a large number of processors and memory modules, due to the requirement of too many connections (switches). Lang proposed a di fferent bus-based system, known as the partial multiple bus system, wh ich requires less number of connections than multiple bus system, but with a slight degradation in system performance. This paper presents a new type of bus-based system, called the multilevel bus system. Such a bus architecture can be used to design hierarchical multiprocessors. This bus-based system requires significantly less number of connectio ns than multiple and partial multiple bus systems. This system is very cost effective, compared to multiple and partial multiple bus systems , when there exists some locality in computations. Analytical and simu lation models have been developed to determine the performance of both synchronous and asynchronous multilevel bus systems. The results obta ined from the analysis show that a multilevel bus system performs fair ly close to other bus-based systems for the hierarchical reference (HR ) model. In the HR model a processor accesses its nearest memory modul es more frequently than other memory modules.