HIGH-LEVEL SYNTHESIS OF VLSI PROCESSORS FOR INTELLIGENT INTEGRATED SYSTEMS

In intelligent integrated systems such as robotics for autonomous work , it is essential to respond to the change of the environment very qui ckly. Therefore, the development of special-purpose VLSI processors fo r intelligent integrated systems with small latency becomes a very imp ortant subject. In this paper, we present a scheduling algorithm for h igh-level synthesis. The input to the scheduler is a behavioral descri ption which is viewed as a data flow graph (DFG). The scheduler minimi zes the latency, which is the delay of the critical path in the DFG, a nd minimizes the number of functional units and buses by improving the utilization rates. By using an integer linear programming, the. sched uler optimally assigns nodes and arcs in the DFG into steps.