THEORETICAL AND EXPERIMENTAL EVALUATION OF HIGH-VOLTAGE CMOS INVERTERS

A high-voltage CMOS technology featuring a 45 V maximum blocking volta ge is described. The transistor output characteristics at high voltage s are simulated by employing an impact-ionisation current model and th e results are verified by measurements on fabricated test structures. Proper inverter operation is maintained up to a supply voltage of 35 V , despite a large impact-ionisation-induced mismatch in the pMOS and n MOS output characteristics at high voltages. In addition, simulation r esults reveal that impact-ionisation currents have little effect on in verter performance in terms of power dissipation. The inverter delay t imes are also found to be independent of the transistor sizes for supp ly voltages of above 25 V; therefore, small-geometry transistors can b e used to reduce the overall area of the high-voltage circuits.