By examining the rate at which successive generations of processor and
DRAM cycle times have been diverging over time, we can track the late
ncy problem of computer memory systems. Our research survey starts wit
h the fundamentals of single-level caches and moves to the need for mu
ltilevel cache hierarchies. we look at some of the current techniques
for boosting cache performance, especially compiler-based methods for
code restructuring and instruction and data prefetching. These two are
as will likely yield improvements for a much larger domain of applicat
ions in the future.