HYBRID SIGNED-DIGIT NUMBER-SYSTEMS - A UNIFIED FRAMEWORK FOR REDUNDANT NUMBER REPRESENTATIONS WITH BOUNDED CARRY PROPAGATION CHAINS

A novel hybrid number representation is proposed in this paper. It inc ludes the two's complement representation and the signed-digit represe ntation as special cases. The hybrid number representations proposed a re capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word len gth. The framework reveals a continuum of number representations betwe en the two extremes of two's complement and signed-digit number system s and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike. We present several s tatic CMOS implementations of a two-operand adder which employ the pro posed representations. We then derive quantitative estimates of area ( in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the trade-offs between area and execution time associated with each of the possible representations. We also discuss adder trees for paralle l multipliers and show that the proposed representations lead to compa ct adder trees with fast execution times. In practice, the area availa ble to a designer is often limited. In such cases, the designer can se lect the particular hybrid representation that yields the most suitabl e implementation (fastest, lowest power consumption, etc.) while satis fying the area constraint. Similarly, if the worst case delay is prede termined, the designer can select a hybrid representation that minimiz es area or power under the delay constraint.