Jb. Evans, EFFICIENT FIR FILTER ARCHITECTURES SUITABLE FOR FPGA IMPLEMENTATION, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 41(7), 1994, pp. 490-493
This paper describes efficient architectures for FIR filters. By explo
iting the reduced complexity made possible by the use of two powers-of
-two coefficients, these architectures allow the implementation of hig
h sampling rate filters of significant length on a single field-progra
mmable gate array (FPGA).