HIGH-SPEED LATCHUP RESISTANT CMOS DATA OUTPUT BUFFER FOR SUBMICROMETER DRAM APPLICATION

A latchup resistant CMOS data output buffer for 0.5 mu m CMOS DRAM is designed, fabricated and measured. It has a floating n-well which adju sts its voltage level to suppress the leakage current. Its leakage cur rent is controlled to be < 10nA with the bonding pad voltage ranging f rom 0 to 10V. The propagation delay is measured to be shorter by 3.8ns than that of an NMOS data output buffer.