DESIGN AND CHARACTERIZATION OF A STANDARD CELL SET FOR DELAY INSENSITIVE VLSI DESIGN

A working synthesis system for delay insensitive (DI) VLSI design is u sed as a case study to investigate the correspondence between theoreti cal formalization and electric circuit operation. Most of the previous research has treated DI VLSI design from a formal point of view. We i llustrate the new features involved in the electrical design and chara cterization of DI cells, reporting circuit schematic and standard cell characterization results. Some integrated circuits built with the cel ls have been fabricated.