Sl. Su et al., A SPACE-EFFICIENT SHORT-FINDING ALGORITHM, IEEE transactions on computer-aided design of integrated circuits and systems, 13(8), 1994, pp. 1065-1068
A common method of locating electrical shorts in VLSI layouts is to bu
ild a connectivity graph of the shorted net and then find the shortest
path between the two offending signals. The memory requirement of thi
s method is proportional to the size of the net, which can be quite la
rge. This paper presents a dynamic graph construction algorithm that s
ignificantly reduces the peak memory requirement. The algorithmic fram
ework allows continuous trade-offs between run times and memory requir
ements.